In this post, you will find a simple, yet easy to use middleware to interface the NAND Flash Memory MT29F2G01ABAGDWB-IT with an STM32 microcontroller using QUADSPI communication . The Micron NAND Flash devices are available in different configurations and densities to fit your project’s needs. It uses SPI and it is a good an alternative solution to SPI NOR, offering superior write performance and cost per bit over SPI NOR.
In our example we are using the HAL QuadSPI API of STM32.
/*!
@file drv_extflash.h
@brief <brief description here>
@t.odo -
---------------------------------------------------------------------------
MIT License
Copyright (c) 2020 Io. D (Devcoons.com)
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/******************************************************************************
* Preprocessor Definitions & Macros
******************************************************************************/
#ifndef DRIVERS_INC_DRV_EXTFLASH_H_
#define DRIVERS_INC_DRV_EXTFLASH_H_
/******************************************************************************
* Includes
******************************************************************************/
#include "quadspi.h"
/******************************************************************************
* Enumerations, structures & Variables
******************************************************************************/
typedef enum
{
I_EXTFLASH_OK = 0x00,
I_EXTFLASH_OK_TX = 0x01,
I_EXTFLASH_OK_RX = 0x02,
I_EXTFLASH_BUSY = 0x10,
I_EXTFLASH_BUSY_TX = 0x11,
I_EXTFLASH_BUSY_RX = 0x12,
I_EXTFLASH_BUSY_PL = 0x13,
I_EXTFLASH_BUSY_CM = 0x14,
I_EXTFLASH_INVALID = 0xFC,
I_EXTFLASH_TIMEOUT = 0xFD,
I_EXTFLASH_ERROR = 0xFE,
I_EXTFLASH_UNKNOWN = 0xFF
}i_status_extflash;
/******************************************************************************
* Declaration | Public Functions
******************************************************************************/
i_status_extflash extflash_status();
i_status_extflash extflash_initialize();
i_status_extflash extflash_erase(uint32_t address);
i_status_extflash extflash_read(uint32_t address, uint8_t* data, uint32_t data_size);
i_status_extflash extflash_write(uint32_t address, uint8_t* data, uint32_t data_size);
/******************************************************************************
* EOF - NO CODE AFTER THIS LINE
******************************************************************************/
#endif/*!
@file drv_extflash.c
@brief <brief description here>
@t.odo -
---------------------------------------------------------------------------
MIT License
Copyright (c) 2020 Io. D (Devcoons.com)
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/******************************************************************************
* Preprocessor Definitions & Macros
******************************************************************************/
/******************************************************************************
* Includes
******************************************************************************/
#include "drv_extflash.h"
/******************************************************************************
* Enumerations, structures & Variables
******************************************************************************/
static volatile i_status_extflash status;
// Ready-made commands and configurations for the quad-spi memory
static QSPI_CommandTypeDef qspi_cmd_get_features =
{
.InstructionMode = QSPI_INSTRUCTION_1_LINE,
.Instruction = 0x0F,
.AddressMode = QSPI_ADDRESS_1_LINE,
.AddressSize = QSPI_ADDRESS_8_BITS,
.Address = 0xc0,
.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE,
.DataMode = QSPI_DATA_1_LINE,
.DummyCycles = 0,
.DdrMode = QSPI_DDR_MODE_DISABLE,
.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY,
.SIOOMode = QSPI_SIOO_INST_EVERY_CMD,
};
static QSPI_AutoPollingTypeDef qspi_cfg_get_features_status_ready =
{
.Match = 0x00,
.Mask = 0x01,
.MatchMode = QSPI_MATCH_MODE_AND,
.StatusBytesSize = 1,
.Interval = 0x10,
.AutomaticStop = QSPI_AUTOMATIC_STOP_ENABLE
};
static QSPI_CommandTypeDef qspi_cmd_reset =
{
.InstructionMode = QSPI_INSTRUCTION_1_LINE,
.Instruction = 0xFF,
.AddressMode = QSPI_ADDRESS_NONE,
.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE,
.DataMode = QSPI_DATA_NONE,
.DummyCycles = 0,
.DdrMode = QSPI_DDR_MODE_DISABLE,
.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY,
.SIOOMode = QSPI_SIOO_INST_EVERY_CMD,
};
static QSPI_CommandTypeDef qspi_cmd_write_enable =
{
.InstructionMode = QSPI_INSTRUCTION_1_LINE,
.Instruction = 0x06,
.AddressMode = QSPI_ADDRESS_NONE,
.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE,
.DataMode = QSPI_DATA_NONE,
.DummyCycles = 0,
.DdrMode = QSPI_DDR_MODE_DISABLE,
.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY,
.SIOOMode = QSPI_SIOO_INST_EVERY_CMD,
};
static QSPI_CommandTypeDef qspi_cmd_erase =
{
.InstructionMode = QSPI_INSTRUCTION_1_LINE,
.Instruction = 0xD8,
.AddressMode = QSPI_ADDRESS_1_LINE,
.AddressSize = QSPI_ADDRESS_24_BITS,
.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE,
.DataMode = QSPI_DATA_NONE,
.DummyCycles = 7,
.DdrMode = QSPI_DDR_MODE_DISABLE,
.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY,
.SIOOMode = QSPI_SIOO_INST_EVERY_CMD,
};
static QSPI_CommandTypeDef qspi_cmd_write =
{
.InstructionMode = QSPI_INSTRUCTION_1_LINE,
.Instruction = 0x32,
.AddressMode = QSPI_ADDRESS_1_LINE,
.AddressSize = QSPI_ADDRESS_16_BITS,
.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE,
.DataMode = QSPI_DATA_4_LINES,
.DummyCycles = 0,
.DdrMode = QSPI_DDR_MODE_DISABLE,
.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY,
.SIOOMode = QSPI_SIOO_INST_EVERY_CMD,
};
static QSPI_CommandTypeDef qspi_cmd_read =
{
.InstructionMode = QSPI_INSTRUCTION_1_LINE,
.Instruction = 0x6B,
.AddressMode = QSPI_ADDRESS_1_LINE,
.AddressSize = QSPI_ADDRESS_16_BITS,
.AlternateByteMode = QSPI_ALTERNATE_BYTES_NONE,
.DataMode = QSPI_DATA_4_LINES,
.DummyCycles = 8,
.DdrMode = QSPI_DDR_MODE_DISABLE,
.DdrHoldHalfCycle = QSPI_DDR_HHC_ANALOG_DELAY,
.SIOOMode = QSPI_SIOO_INST_EVERY_CMD,
};
/******************************************************************************
* Declaration | Static Functions
******************************************************************************/
/******************************************************************************
* Definition | Static Functions
******************************************************************************/
/******************************************************************************
* Definition | Public Functions
******************************************************************************/
i_status_extflash extflash_initialize()
{
if(status != I_EXTFLASH_OK)
return status;
status = I_EXTFLASH_BUSY;
if (HAL_QSPI_Command(&hqspi, &qspi_cmd_reset, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
goto ret_extflash_initialize_error;
if (HAL_QSPI_AutoPolling_IT(&hqspi, &qspi_cmd_get_features, &qspi_cfg_get_features_status_ready) != HAL_OK)
goto ret_extflash_initialize_error;
return status;
ret_extflash_initialize_error:
status = I_EXTFLASH_ERROR;
return status;
}
i_status_extflash extflash_erase(uint32_t address)
{
if(status != I_EXTFLASH_OK)
return status;
status = I_EXTFLASH_BUSY;
if (HAL_QSPI_Command(&hqspi, &qspi_cmd_write_enable, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
goto ret_extflash_erase_error;
qspi_cmd_erase.Address = address;
if (HAL_QSPI_Command(&hqspi, &qspi_cmd_erase,HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
goto ret_extflash_erase_error;
status = I_EXTFLASH_BUSY_PL;
if (HAL_QSPI_AutoPolling_IT(&hqspi, &qspi_cmd_get_features, &qspi_cfg_get_features_status_ready) != HAL_OK)
goto ret_extflash_erase_error;
return status;
ret_extflash_erase_error:
status = I_EXTFLASH_ERROR;
return status;
}
i_status_extflash extflash_write(uint32_t address, uint8_t* data, uint32_t data_size)
{
if(status != I_EXTFLASH_OK)
return status;
status = I_EXTFLASH_BUSY_TX;
if (HAL_QSPI_Command(&hqspi, &qspi_cmd_write_enable, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
goto ret_extflash_write_error;
qspi_cmd_write.NbData = data_size;
qspi_cmd_write.Address = address;
if (HAL_QSPI_Command(&hqspi, &qspi_cmd_write, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
goto ret_extflash_write_error;
if (HAL_QSPI_Transmit_IT(&hqspi, data) != HAL_OK)
goto ret_extflash_write_error;
return status;
ret_extflash_write_error:
status = I_EXTFLASH_ERROR;
return status;
}
i_status_extflash extflash_read(uint32_t address, uint8_t* data, uint32_t data_size)
{
if(status != I_EXTFLASH_OK)
return status;
status = I_EXTFLASH_BUSY_RX;
qspi_cmd_read.NbData = data_size;
qspi_cmd_read.Address = address;
if (HAL_QSPI_Command(&hqspi, &qspi_cmd_read, HAL_QPSI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)
goto ret_extflash_read_error;
if (HAL_QSPI_Receive_IT(&hqspi, data) != HAL_OK)
goto ret_extflash_read_error;
return status;
ret_extflash_read_error:
status = I_EXTFLASH_ERROR;
return status;
}
i_status_extflash extflash_status()
{
switch(HAL_QSPI_GetState(&hqspi))
{
case HAL_QSPI_STATE_RESET:
status = I_EXTFLASH_UNKNOWN;
break;
case HAL_QSPI_STATE_ERROR:
status = I_EXTFLASH_ERROR;
break;
default:
break;
}
return status;
}
/// QSPI Callback function
void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
{
status = I_EXTFLASH_BUSY_PL;
if (HAL_QSPI_AutoPolling_IT(hqspi, &qspi_cmd_get_features, &qspi_cfg_get_features_status_ready) != HAL_OK)
status = I_EXTFLASH_ERROR;
}
void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
{
status = I_EXTFLASH_BUSY_PL;
if (HAL_QSPI_AutoPolling_IT(hqspi, &qspi_cmd_get_features, &qspi_cfg_get_features_status_ready) != HAL_OK)
status = I_EXTFLASH_ERROR;
}
void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
{
status = I_EXTFLASH_OK;
}
/******************************************************************************
* EOF - NO CODE AFTER THIS LINE
******************************************************************************/
*
* TESTED WITH THE FOLLOWING EXAMPLE
*/
uint8_t data[128];
extflash_initialize();
while(extflash_status()!= I_EXTFLASH_OK)
HAL_Delay(10);
extflash_erase(0);
while(extflash_status()!= I_EXTFLASH_OK)
HAL_Delay(10);
extflash_read(0, data, 8);
while(extflash_status()!= I_EXTFLASH_OK)
HAL_Delay(10);
extflash_write(0x10, "01234567890123456", 16);
while(extflash_status()!= I_EXTFLASH_OK)
HAL_Delay(10);
extflash_read(0x10, data, 64);
while(extflash_status()!= I_EXTFLASH_OK)
HAL_Delay(10);
I was looking some help for this flash memory! Nice post!
Thanks